1. Field of the Invention
The present invention relates to a field effect transistor type ferroelectric nonvolatile storage element using a ferroelectric body at a control gate and a method of fabricating the same.
2. Description of the Related Art
As a field effect transistor type ferroelectric nonvolatile storage element using a ferroelectric body at a control gate, there is MFS-FET (Metal-Ferroelectric-Semiconductor-field effect transistor) (or conductor layer-ferroelectric layer-semiconductor-field effect transistor) having a constitution of replacing an oxide film constituting an insulating layer of normal MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) (or conductor layer-oxide film-semiconductor-field effect transistor) by a ferroelectric body. According to the MFS-FET type memory, there is provided a method in which polarization of a ferroelectric body changes threshold voltage of the transistor and a change in resistance of a channel between a source and a drain is read as a change in the magnitude of a drain current value. According to the system, there is constituted so-to-speak nondestructive reading in which information is not destructed by reading operation at low voltage since ON/OFF of FET (field effect transistor) is maintained by holding residual polarization of the ferroelectric body.
A field effect ferroelectric memory transistor (MFS-FET) arranging a ferroelectric body at a control gate is classified into two kinds in gross classification. One of them is a ferroelectric transistor having a structure of MFIS (Metal-Ferroelectric-Insulator-Semiconductor) (or conductor layer-ferroelectric layer-insulator layer-semiconductor), in which an insulating layer (I) is sandwiched between a ferroelectric layer (F) and a semiconductor (S) of an MFS structure. The ferroelectric body induces electric charge at a surface of a semiconductor substrate via a gate insulating layer by polarization thereof.
Other thereof is a ferroelectric transistor having a structure of MFMIS (Metal-Ferroelectric-Metal-Insulator-Semiconductor) (or conductor layer-ferroelectric layer-conductor layer-insulating layer-semiconductor) as a gate structure, in which a conductor layer (M) (or referred to as floating gate) is sandwiched between a ferroelectric layer (F) and an insulating layer (I) of an MFIS structure. The present invention relates to the latter of the MFMIS structure.
Further, a conductor layer (M) described in the specification includes a conductor of polycrystal silicon (polysilicon, Poly-Si), an alloy of a metal and polycrystal silicon or the like other than a metal and a laminate thereof.
According to a conventional MFMIS type ferroelectric memory, as shown by FIG. 12A, there are formed a source region and a drain region by interposing a channel region on a semiconductor substrate (S), a main face of the middle channel region of the semiconductor substrate (S) is laminated with a silicon oxide layer (SiO2) frequently used in a semiconductor process as a gate insulator layer (I), polysilicon (Poly-Si) is laminated thereon as a first conductor layer (M), Ir/IrO2 (iridium/iridium oxide) is laminated further thereon as a barrier layer for preventing mutual diffusion between a ferroelectric material and Poly-Si, a ferroelectric thin layer (F), for example, PZT (PbZrxTi1-xO3) is laminated thereon and as a gate electrode, Ir/IrO2 is laminated thereon as a second conductor layer (M). FIG. 12A shows the laminated structure as a gate portion formed by carrying out lithography and etching. (A reference: T. Nakamura et al. Dig. Tech. Pap. of 1995 IEEE Int. Solid State Circuits Conf. p. 68 (1995))
FIG. 12B shows the MFMIS structure of FIG. 12A by an equivalent circuit and a capacitance (CF) of a ferroelectric capacitor and a capacitance (CI) of a gate insulator capacitor are connected in series. In FIG. 12B, when the ferroelectric layer is polarized by applying voltage between an upper electrode A and a semiconductor substrate B, it is necessary to apply the voltage until polarization of the ferroelectric body is sufficiently saturated in view of a memory holding characteristic.
Voltage distributed to the ferroelectric capacitor is dependent on a coupling ratio (CI/(CI+CF)) between the capacitance (CF) of the ferromagnetic capacitor and the capacitance (CI) of the gate insulator capacitor.
In order to enlarge the voltage distributed to the ferroelectric capacitor, it is important to design such that the capacitance (CI) of the gate insulating capacitor becomes larger than the capacitance (CF) of the ferroelectric capacitor.
Hence, in order to design to make the capacitance (CI) of the gate insulator capacitor larger than the capacitance (CF) of the ferroelectric capacitor, it is conceivable to thin the gate insulating film and thicken the ferroelectric thin film, however, there is a limit in thinning the gate insulating film in view of withstand voltage and leakage current. Further, when the ferroelectric thin film is thickened, high drive voltage is needed to saturate polarization of the ferroelectric body.
A conventional method for making the capacitance (CI) of the gate insulator capacitor larger than the capacitance (CF) of the ferroelectric capacitor while avoiding these problems, is a method of changing areas of the capacitance CF and the capacitance CI. FIG. 12C shows a simple schematic sectional view of carrying out the method. FIG. 12D shows a plain view viewing FIG. 12C from above. There is provided an MFMIS structure having a ferroelectric layer only at portion of an area of an MIS (conductor-insulator-semiconductor) portion for constituting CI. CI can be designed to be larger than CF as necessary by the conventional method.
However, according to the conventional method, in order to apply large distributed voltage on the ferroelectric capacitor, there is adopted the method of planarly enlarging the area of the MIS capacitor relative to the area of the MFM capacitor and therefore, as shown by FIG. 12D, even when the MFMIS portion is formed by a minimum fabrication dimension, the MIS portion is as large as an amount of an area ratio of the MIS portion and the MFMIS portion, as a result, a large area is occupied and there poses a problem that a high integration degree cannot be achieved.